1. Field
Example embodiments relate to a semiconductor device and methods of manufacturing and operating the same. Other example embodiments relate to a capacitorless DRAM and methods of manufacturing and operating the same.
2. Description of the Related Art
A memory cell of a conventional dynamic random access memory (DRAM) has a 1T/1C structure (i.e., one transistor and one capacitor). It may be difficult to decrease a cell area of a conventional DRAM that includes both a transistor and a capacitor.
In order to scale down conventional DRAMs, a DRAM that stores data with a transistor and without a capacitor (e.g., a capacitorless 1T DRAM) has been disclosed. A conventional capacitorless 1T DRAM may have an electrically floated channel.
FIGS. 1A and 1B are diagrams illustrating cross-sectional views of a conventional capacitorless 1T DRAM.
Referring to FIGS. 1A and 1B, a gate 110 may be formed on a silicon on insulator (SOI) substrate 100. The SOI substrate 100 may have a structure in which a first silicon layer 10, an oxide layer 20 and a second silicon layer 30 are sequentially stacked. The gate 110 may have a structure in which a gate insulating layer 40 and a gate conductive layer 50 are sequentially stacked. A source 30a and a drain 30b may be formed in the second silicon layer 30 on both sides of the gate 110. A floating channel body 30c, which is electrically separated from the first silicon layer 10, may be located (or formed) in the second silicon layer 30 between the source 30a and the drain 30b. 
As depicted in FIG. 1A, if 0.6V, 0V, and 2.3V are respectively applied to the gate conductive layer 50, the source 30a and the drain 30b, then electrons migrate from the source 30a to the drain 30b through the floating channel body 30c. Electron-hole pairs may be generated in the floating channel body 30c due to electron impact. The generated holes accumulate in the floating channel body 30c and cannot migrate to the outside. The holes generated in this manner are referred to as excess holes 5. The state in which the excess holes 5 accumulate in the floating channel body 30c is referred to as a first state.
As depicted in FIG. 1B, if 0.6V, 0V, and −2.3V are respectively applied to the gate conductive layer 50, the source 30a and the drain 30b, then a forward bias is applied between the floating channel body 30c and the drain 30b. The excess holes 5 may be removed (or migrate) from the floating channel body 30c and excess electrons 7 may accumulate in the floating channel body 30c. The state in which the excess electrons 7 accumulate in the floating channel body 30c is referred to as a second state.
Because the electrical resistances in the first and second states of the floating channel body 30c differ from each other, the first and second states can correspond to data values ‘1’ and ‘0’, respectively.
In the conventional capacitorless 1T DRAM, the data retention characteristic in the floating channel body 30c may not be acceptable. In the conventional capacitorless 1T DRAM, because a substantially large area of the floating channel body 30c contacts the source 30a and the drain 30b, a large number of charges may leak at junction areas therebetween. As such, data retention time in the floating channel body 30c may decrease.
If the length of the floating channel body 30c is reduced in order to scale down the conventional capacitorless 1T DRAM, the doping concentration in the floating channel body 30c must be increased to secure a threshold voltage. As the junction leakage current between the floating channel body 30c and the source 30a and the drain 30b increases, the data retention characteristic decreases.
The conventional capacitorless 1T DRAM may be a planar type device. If the length of the floating channel body 30c is reduced below a critical value, interference between the source 30a and the drain 30b (i.e., a short channel effect) may occur. The operating characteristics of the device may be degraded. As such, it may be difficult to scale down a conventional capacitorless 1T DRAM.